Digitally controlled oscillators (DCO) are increasingly being used in phase locked loop (PLL) systems in a variety of applications. The basic, digitally controlled oscillator employs a divide-by-N counter, to which fixed frequency clock pulses are applied. The loop filter of the phase locked loop, in which the system is used, provides signals to the divide-by-N counter to cause the output signal to comprise a division in which the output frequency consists of an even number of input clock pulses. The output waveform has a symmetrical duty cycle; but the resolution is limited by the frequency of the clock signals, and the necessity for an even number of clock signals to appear in each cycle of the
A modified divide-by-N counter has been developed, which provides greater resolution than the above-described divide-by-N counter. Such a modified divide-by-N counter is capable of producing an output frequency of any number of clocks (odd or even). The result is that the duty cycle of the output signal is not always symmetrical; but for phase locked loop systems this generally is not a factor. Although a significant improvement in the foregoing system is provided with such a modified divide-by-N counter system, it still is necessary for each half-cycle of the output waveform to comprise an integral number of complete clock waveform cycles. For example, one-half cycle of the output waveform could include two full cycles of the input clock signal; and the other half-cycle of the output waveform could include three full cycles of the input clock signal, for a total of five clock signals for each complete cycle of the output waveform. The system also is capable of producing symmetrical waveforms, in which the same number of clock pulses or clock signal cycles are present in each half of the divided-down output waveform cycle.
Other types of digitally controlled oscillators have been developed, such as increment/decrement counters and waveform synthesizers. The increment/decrement counter operates in conjunction with loop filters, which generate carry and borrow pulses. In the absence of any carry and borrow pulses, the counter divides the input frequency by a factor of 2. Whenever a carry pulse appears at the input, an additional clock cycle is added by the increment/decrement counter. Similarly, whenever a borrow pulse appears on the input, the increment/decrement counter deletes a clock cycle from the output produced by the counter. It is readily apparent that the output frequency of the digitally controlled oscillator, therefore, is controllable within a range given by the maximum frequency of the carry and borrow pulses.
Waveform synthesizers are complex to implement in hardware. Consequently, they are most suited for software implementation. The counter or divider circuit for a waveform synthesizer type of digitally controlled oscillator operates at a fixed clock rate or sampling rate to calculate a sample of the synthesized signal at the different sampling instants. A system of this type produces lower frequency signals, with higher resolution than higher frequency signals. It is desirable to provide a digitally controlled oscillator circuit, which is relatively easy to implement in hardware, and which provides a higher resolution than the prior art digitally controlled oscillators or frequency divider circuits discussed above.